View KM48C2004C_4772090.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c this is a family of 2,097,152 x 8 bit extended data out cmos drams. extended data out mode offers high speed random access of memory cells within the same row, so called hyper page mode. power supply voltage (+5.0v or +3.3v), refresh cycle (2k ref. or 4k ref.), access time (-5 or -6), power consumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. all of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self-refresh operation is available in l-version. this 2mx8 edo mode dram family is fabricated using samsung s advanced cmos process to real- ize high band-width, low power consumption and high reliability. it may be used as graphic memory unit for microcomputer and per sonal computer. ? part identification - KM48C2004C/c-l (5v, 4k ref.) - km48c2104c/c-l (5v, 2k ref.) - km48v2004c/c-l (3.3v, 4k ref.) - km48v2104c/c-l (3.3v, 2k ref.) ? extended data out mode operation (fast page mode with extended data out) ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? fast parallel test mode capability ? ttl(5v)/lvttl(3.3v) compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in plastic soj and tsop(ii) packages ? single +5v 10% power supply (5v product) ? single +3.3v 0.3v power supply (3.3v product) control clocks ras cas w vcc vss dq0 to dq7 a0-a11 (a0 - a10) *1 a0 - a8 (a0 - a9) *1 memory array 2,097,152 x8 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 2m x 8bit cmos dynamic ram with extended data out description features functional block diagram ? refresh cycles part no. v cc refresh cycle refresh period normal l-ver c2004c 5v 4k 64ms 128ms v2004c 3.3v c2104c 5v 2k 32ms v2104c 3.3v ? performance range speed t rac t cac t rc t hpc remark -5 50ns 13ns 84ns 20ns 5v/3.3v -6 60ns 15ns 104ns 25ns 5v/3.3v ? active power dissipation speed 3.3v 5v 4k 2k 4k 2k -5 324 396 495 605 -6 288 360 440 550 unit : mw s e n s e a m p s & i / o data out buffer data in buffer oe note) *1 : 2k refresh col. address buffer row address buffer refresh counter refresh control refresh timer column decoder row decoder vbb generator
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c v cc dq0 dq1 dq2 dq3 w ras *a11(n.c) a10 a0 a1 a2 a3 v cc v ss dq7 dq6 dq5 dq4 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin configuration (top views) pin name pin function a0 - a11 address inputs (4k product) a0 - a10 address inputs (2k product) dq0 - 7 data in/out v ss ground ras row address strobe cas column address strobe w read/write input oe data output enable v cc power(+5v) power(+3.3v) n.c no connection (2k ref. product) v cc dq0 dq1 dq2 dq3 w ras *a11(n.c) a10 a0 a1 a2 a3 v cc v ss dq7 dq6 dq5 dq4 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 *a11 is n.c for km48c/v2104c(5v/3.3v, 2k ref. product) k : 300mil 28 soj s : 300mil 28 tsop ii ? km48c/v20(1)04ck ? km48c/v20(1)04cs
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol rating units 3.3v 5v voltage on any pin relative to v ss v in, v out -0.5 to +4.6 -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -0.5 to +4.6 -1.0 to +7.0 v storage temperature tstg -55 to +150 -55 to +150 c power dissipation p d 1 1 w short circuit output current i os address 50 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +1.3v/15ns(3.3v), v cc +2.0v/20ns(5v), pulse width is measured at v cc *2 : -1.3v/15ns(3.3v), -2.0v/20ns(5v), pulse width is measured at v ss parameter symbol 3.3v 5v units min typ max min typ max supply voltage v cc 3.0 3.3 3.6 4.5 5.0 5.5 v ground v ss 0 0 0 0 0 0 v input high voltage v ih 2.0 - v cc +0.3 *1 2.4 - v cc +1.0 *1 v input low voltage v il -0.3 *2 - 0.8 -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) max parameter symbol min max units 3.3v input leakage current (any input 0 v in v in +0.3v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-2ma) v oh 2.4 - v output low voltage level(i ol =2ma) v ol - 0.4 v 5v input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 and i cc6, address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one hyper page mode cycle time, t hpc . dc and operating characteristics (continued) i cc1 * : operating current ( ras and cas cycling @t rc =min.) i cc2 : standby current ( ras = cas = w =v ih ) i cc3 * : ras -only refresh current ( cas =v ih , ras cycling @t rc =min.) i cc4 * : hyper page mode current ( ras =v il , cas , address cycling @t hpc =min.) i cc5 : standby current ( ras = cas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras and cas cycling @t rc =min.) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, cas =0.2v, dq=don t care, t rc =31.25us(4k/l-ver), 62.5us(2k/l-ver), t ras =t ras min~300ns i ccs : self refresh current ras = cas =v il , w = oe =a0 ~ a11=v cc -0.2v or 0.2v, dq0 ~ dq7=v cc -0.2v, 0.2v or open symbol power speed max units km48v2004c km48v2104c KM48C2004C km48c2104c i cc1 don t care -5 -6 90 80 110 100 90 80 110 100 ma ma ma i cc2 normal l don t care 1 1 1 1 2 1 2 1 ma ma i cc3 don t care -5 -6 90 80 110 100 90 80 110 100 ma ma ma i cc4 don t care -5 -6 80 70 90 80 80 70 90 80 ma ma ma i cc5 normal l don t care 0.5 200 0.5 200 1 250 1 250 ma ua i cc6 don t care -5 -6 90 80 110 100 90 80 110 100 ma ma ma i cc7 l don t care 250 250 300 300 ua i ccs l don t care 200 200 250 250 ua
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c capacitance (t a =25 c, v cc =5v or 3.3v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a11] c in1 - 5 pf input capacitance [ ras , cas , w , oe ] c in2 - 7 pf output capacitance [dq0 - dq7] c dq - 7 pf test condition (5v device) : v cc =5.0v 10%, vih/vil=2.4/0.8v, voh/vol=2.0/0.8v parameter symbol -5 -6 units notes min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 116 140 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 13 15 ns 3,4,5 access time from column address t aa 25 30 ns 3,10 cas to output in low-z t clz 3 3 ns 3 output buffer turn-off delay from cas t cez 3 13 3 15 ns 6,14 oe to output in low-z t olz 3 3 ns 3 transition time (rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 13 15 ns cas hold time t csh 38 45 ns cas pulse width t cas 8 10k 10 10k ns ras to cas delay time t rcd 20 37 20 45 ns 4 ras to column address delay time t rad 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set-up time t asc 0 0 ns column address hold time t cah 8 10 ns column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 8 read command hold time referenced to ras t rrh 0 0 ns 8 write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 8 10 ns ac characteristics (0 c t a 70 c, see note 1,2) test condition (3.3v device) : v cc =3.3v 0.3v, vih/vil=2.0/0.8v, voh/vol=2.0/0.8v
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c ac characteristics (continued) parameter symbol -5 -6 units notes min max min max data set-up time t ds 0 0 ns 9 data hold time t dh 8 10 ns 9 refresh period (2k, normal) t ref 32 32 ms refresh period (4k, normal) t ref 64 64 ms refresh period (l-ver) t ref 128 128 ms write command set-up time t wcs 0 0 ns 7 cas to w delay time t cwd 30 34 ns 7 ras to w delay time t rwd 67 79 ns 7 column address to w delay time t awd 42 49 ns 7 cas precharge to w delay time t cpwd 47 54 ns cas set-up time ( cas -before- ras refresh) t csr 5 5 ns cas hold time ( cas -before- ras refresh) t chr 10 10 ns ras to cas precharge time t rpc 5 5 ns access time from cas precharge t cpa 28 35 ns 3 hyper page cycle time t hpc 20 25 ns 13 hyper page read-modify-write cycle time t hprwc 47 56 ns 13 cas precharge time (hyper page cycle) t cp 8 10 ns ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns oe access time t oea 13 15 ns oe to data delay t oed 13 15 ns output buffer turn off delay time from oe t oez 3 13 3 15 ns 6 oe command hold time t oeh 13 15 ns write command set-up time (test mode in) t wts 10 10 ns 11 write command hold time (test mode in) t wth 10 10 ns 11 w to ras precharge time( c -b- r refresh) t wrp 10 10 ns w to ras hold time( c -b- r refresh) t wrh 10 10 ns output data hold time t doh 5 5 ns output buffer turn off delay from ras t rez 3 13 3 15 ns 6,14 output buffer turn off delay from w t wez 3 13 3 15 ns 6 w to data delay t wed 15 15 ns oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width (hyper page cycle) t wpe 5 5 ns ras pulse width ( c -b- r self refresh) t rass 100 100 us 15,16,17 ras precharge time ( c -b- r self refresh) t rps 90 110 ns 15,16,17 cas hold time ( c -b- r self refresh) t chs -50 -50 ns 15,16,17
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c test mode cycle parameter symbol -5 -6 units note min max min max random read or write cycle time t rc 89 109 ns read-modify-write cycle time t rwc 121 145 ns access time from ras t rac 55 65 ns 3,4,10,12 access time from cas t cac 18 20 ns 3,4,5,12 access time from column address t aa 30 35 ns 3,10,12 ras pulse width t ras 55 10k 65 10k ns cas pulse width t cas 13 10k 15 10k ns ras hold time t rsh 18 20 ns cas hold time t csh 43 50 ns column address to ras lead time t ral 30 35 ns cas to w delay time t cwd 35 39 ns 7 ras to w delay time t rwd 72 84 ns 7 column address to w delay time t awd 47 54 ns 7 cas precharge to w delay time t cpwd 52 59 ns hyper page cycle time t hpc 25 30 ns 13 hyper page read-modify-write cycle time t hprwc 53 61 ns 13 ras pulse width (hyper page cycle) t rasp 55 200k 65 200k ns access time from cas precharge t cpa 33 40 ns 3 oe access time t oea 18 20 ns oe to data delay t oed 18 20 ns oe command hold time t oeh 18 20 ns ( note 11 )
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c notes an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 2ns for all inputs. measured with a load equivalent to 2 ttl(5v)/1 ttl(3.3v) loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the data sheet as electrical char- acteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min) and t awd 3 t awd (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to cas falling edge in early write cycles and to w falling edge in oe controlled write cycle and read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . these specifications are applied in the test mode. in test mode read cycle, the value of t rac , t aa , t cac is delayed by 2ns to 5ns for the specified values. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. t asc 3 6ns, assume t t = 2.0ns if ras goes high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes high before ras high going, the open circuit condition of the output is achieved by ras high going. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 4096(4k)/2048(2k) cycles of burst refresh must be exe- cuted within 64ms/32ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 1. 2. 3. 4. 17.
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t oea t clz t rac open t rch don t care undefined t rad t rrh data-out t rez t rcs read cycle t oez t cez t wez dq0 ~ dq3(7) t olz t cac
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c t wcs note : d out = open write cycle ( early write ) ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care undefined t wch t wp cas t rwl t cwl t ds t dh data-in dq0 ~ dq3(7)
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c note : d out = open write cycle ( oe controlled write ) ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp don t care undefined cas v ih - v il - t rwl t cwl t dh t oeh t oed data-in t ds
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c read - modify - write cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address t olz
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c t doh hyper page read cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care undefined v oh - v ol - dq0 ~ dq3(7) t oep column address t cas t cas t cas t cas t cp t cp t cp t hpc t hpc t hpc t rhcp t csh t rad t rah t asc t cah t cah t cah t asc t cah t rcs t aa t rch t asc column address column addr valid data-out t oez t oea t oep t aa t cac t aa t cpa t cpa valid data-out valid data-out t oez t clz t rac t oea t olz t cac t rrh t cho t rez t oez t cac t och t cpa t cac valid data-out ? t asc t aa t ral t oea
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page write cycle ( early write ) undefined v ih - v il - dq0 ~ dq3(7) t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh t cwl t cwl t cwl t rwl note : d out = open t hpc t hpc t wcs t ral
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c don t care hyper page read-modify-write cycle undefined ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - row addr t csh t rasp t rp t asr t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t rac t oea t clz t oez t cpwd t oed t asc t clz t oea t cac t aa t dh t oed t rwl t crp t ds t oez valid data-out valid data-in valid data-out valid data-in t ds dq0 ~ dq3(7) t rsh t olz t olz t hprwc t cac t aa t rah
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c hyper page read and write mixed cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp don t care undefined v i/oh - v i/ol - dq0 ~ dq3(7) t wez t cp t cp t hpc t hpc t hpc t rad t rah t asc t cah t cah t cah t asc t cah t rch t rcs t rcs t rch t asc column address col. addr valid data-out t rez t aa t wcs valid data-out valid data-out valid data-in t rac col. addr t cas t asr t cas t cas t cas t asc t cp t rch t wch t wpe t clz t cpa t wed t aa t wez t ds t dh t cac t oea read( t cac ) read( t cpa ) write read( t aa ) t rhcp t ral t clz
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c don t care ras - only refresh cycle* note : w , oe , d in = don t care undefined d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp t ras t rah t rpc t crp open cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rc t rp t ras t rpc t cp t rpc t csr t chr t cez v oh - v ol - dq0 ~ dq3(7) t wrp t wrh w v ih - v il - t rp
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c hidden refresh cycle ( read ) t oez data-out t rp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care undefined v oh - v ol - dq0 ~ dq3(7) t wrh column address t oea t ras t rc t cah t rcs t aa t rac t clz t cac t cez open t rp t wez t rez t olz t ral
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c t crp t wcs t rp ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t rad t asr t rah t asc don t care hidden refresh cycle ( write ) undefined cas v ih - v il - v ih - v il - dq0 ~ dq3(7) t rsh t rcd t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t rp t ral
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rps t rass t rpc t cp t rpc t csr t cez v oh - v ol - dq0 ~ dq3(7) t rp don t care undefined t chs t wrp t wrh w v ih - v il - open test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rp t rc t rpc t cp t rpc t csr t off v oh - v ol - dq0 ~ dq3(7) t wts t wth w v ih - v il - t chr t rp t ras
KM48C2004C, km48c2104c cmos dram km48v2004c, km48v2104c package dimension 28 soj 300mil 0 . 3 0 0 ( 7 . 6 2 ) 0 . 3 3 0 ( 8 . 3 9 ) 0 . 3 4 0 ( 8 . 6 3 ) 0.730 (18.54) 0.720 (18.30) max 0.741 (18.82) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.0375 (0.95) 0.050 (1.27) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 2 8 0 ( 7 . 1 1 ) 0 . 2 6 0 ( 6 . 6 1 ) min #28 #1 units : inches (millimeters) 28 tsop(ii) 300mil max 0.047 (1.20) min 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) 0.050 (1.27) 0.037 (0.95) 0.721 (18.31) 0.729 (18.51) 0.741 (18.81) max 0.010 (0.25) 0.004 (0.10) 0 . 3 0 0 ( 7 . 6 2 ) 0 . 3 7 1 ( 9 . 4 2 ) 0 . 3 5 5 ( 9 . 0 2 ) units : inches (millimeters) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o

▲Up To Search▲

Price & Availability of KM48C2004C

	To Download KM48C2004C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .